The invention relates to integrated circuits (ICs), and more particularly to virtual architectures in a parallel processing environment.
FPGAs (Field Programmable Gate Arrays) and ASICs (Application Specific Integrated Circuits) are two exemplary approaches for implementing customized logic circuits. An ASIC is designed for a specific application. The cost of building an ASIC includes the cost of verification, the cost of physical design and timing closure, and the NRE (non-recurring costs) of creating mask sets and fabricating the ICs. Due to the increasing costs of building an ASIC, FPGAs became increasingly popular in the late 1990's. Unlike an ASIC, an FPGA is reprogrammable in that it can be reconfigured for each application. Similarly, as protocols change, an FPGA design can be changed even after the design has been shipped to customers, much like software can be updated. However, FPGAs are typically more expensive, often costing 10 to 100 times more than an ASIC. FPGAs are typically power hungry and their performance can be 10 to 20 times worse than that of an ASIC.
The Massachusetts Institute of Technology (MIT) Raw integrated circuit design provides reconfigurability of an FPGA along with the performance and capability of an ASIC. The Raw design is an example of a tiled integrated circuit providing a computational substrate as described for example, in “Baring It All to Software: RAW Machines” IEEE Computer, September 1997, pp. 86-93. The Raw design can be used to exploit fine-grained Instruction-Level Parallelism (ILP) in a program to execute the program using the parallel processing resources of the integrated circuit.
In some processor architectures, such as a Very Long Instruction Word (VLIW) processor architecture, applications such as dynamic translation of instructions from one instruction set architecture to another can exploit ILP to map translated code across parallel resources of the VLIW, increasing translation speed. However, this fine-grained parallelism does not necessarily enable the application to use the parallel resources for a more coarse-grained division of the application functions across the computational substrate.